In a conventional layout process for a mask pattern for a semiconductor integrated circuit, a layout device automatically generates a mask layout diagram indicating the physical layout of a mask pattern or wiring for an integrated circuit based on a logically verified circuit netlist. Since a circuit diagram has no practical physical information, the physical positional relationship in the mask pattern are given only through the layout process. In most cases, the physical positions of the mask pattern in the layout are based on timing information on logical operations of the integrated circuit.
If, for example, fine foreign matter adheres to a mask during an integrated circuit manufacturing process, a defect such as a pattern bridge occurs in that portion to which the foreign matter adheres. Such a defect is generally detected by using predetermined test patterns in an integrated circuit detecting step to examine input and output signals. An automatic test pattern generator (ATPG) is also known which automatically generates such test patterns based on information such as a circuit diagram.
In an advanced integrated circuit, however, the number of test patterns executed is limited due to a limitation on an detection time associated with costs. Thus, it is important to promptly and efficiently detect a defect (hereafter referred to as a “fault”) in the integrated circuit. Accordingly, it is necessary to determine the probability of detecting faults in the integrated circuit using certain test patterns, that is, to evaluate a fault coverage. The evaluation of the fault coverage is referred to as “fault detection” herein. The term “fault detection” herein is sometimes used to express its original meaning, that is, detection for faults.
With a conventional fault detection, the fault coverage is output using a circuit netlist, or fault list and test patterns. Specifically, the fault detecting means (ATPG) allows a fault state to be artificially created in an interacted circuit, which is then processed by a tester (or a fault detector) to determine whether or not that fault is normally detected (fault simulation).
The fault list is not only loaded but may also be output as a detection result. The fault detecting means (ATPG) uses the circuit netlist or the fault list to automatically generate test patterns, and may also output the fault coverage.
Due to a recent increase in the scale of integrated circuits, an enormous amount of test patterns and a large amount of processing time for fault simulation for the test patterns are required to obtain a high fault coverage. An enormous amount of processing time is also required for the ATPG and a large amount of test patterns are automatically generated by the ATPG. On the other hand, a required fault coverage is increasing in order to improve the reliability of the integrated circuit.
When a phenomenon that may cause a fault, for example, adhesion of foreign matter to a mask occurs in a physical area on a chip, this may lead to a fault if the foreign matter sticks to a portion where a mask pattern is present. There are portions in the chip where no mask pattern is present, and no fault occurs even if the foreign matter adheres to these portions.
Typically, the mask pattern is not uniformly present on the chip; the mask pattern is dense in some areas, while it is coarse in the other areas. Consequently, if a phenomenon that may cause a fault occurs substantially uniformly on the chip, the probability of an actual fault occurring is not uniform on the chip, but the fault occurrence rate is higher in a dense portion in the mask pattern than in a coarse portion in the mask pattern.
On the other hand, when, for example, a mask portion for a normal signal line is close to a mask portion for a power line, the integrated circuit is likely to malfunction due to a possible noise from a power supply. If signal lines are close to each other, the integrated circuit is also likely to malfunction because a signal of a lower intensity is affected by a signal of a higher intensity.
Thus, the probability of an actual fault occurring varies depending on mask conditions, that is, the layout, wiring, and the type of the mask.
Furthermore, the possibility of a fault occurring increases if a new process, a newly developed cell, or a cell or functional block the reliability of which has not been proved is used.
The conventional fault detection uses only the circuit netlist and test patterns and does not take the circuit layout or the records of use of cells or functional blocks into consideration. That is, the fault simulation is carried out by assuming the possibility of an actual fault occurring for each fault to be subjected to detection to be constant, so that the conventional fault coverage may not be accurate enough to be an actual index of the fault occurrence rate. In addition, the conventional fault detection is inefficient because it does not subject actually likely faults to the fault detection or the ATPG before less likely faults.
Additionally, due to the ever increasing scale and decreasing size of recent integrated circuits, there are expected to be new faults that cannot be expressed by a conventional single stuck-at fault model. That is, the relationship between a defect level in the market and the fault coverage may not be expressed by a simple equation such as that described later. A new measure for the fault coverage is thus required which takes actual faults occurring into account.
Furthermore, the conventional layout method does not take the likelihood of faults into consideration and takes no mask layout measures for preventing faults.